EN2340QI Datasheet, PDF (3/23 Pages) Enpirion, Inc. – 204A Voltage Mode Synchronous Buck PWM

PIN
61-63
29-34
35-41
42
43
44
45
46
47
48
49
50
51
52, 53,
60
54
55
56
57
58
69
EN2340QI
NAME I/O
FUNCTION
internal MOSFETs. They are not to be electrically connected to any external signal, ground,
or voltage. Failure to follow this guideline may result in damage to the device.
PGND
G
Input/output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
PVIN
P
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND pins 29-34.
Internal 3.3V linear regulator output. Connect this pin to AVIN (Pin 51) for applications
AVINO
O
where operation from a single input voltage (PVIN) is required. If AVINO is being used,
place a 1µF, X5R/X7R, capacitor between AVINO and AGND as close as possible to
AVINO.
PMOS gate. Place a 22nF, X5R/X7R, capacitor between this pin and BTMP. A 560Ω
PG I/O damping resistor may be connected from PVIN to PG to reduce noise inside the controller
in extreme ambient conditions.
BTMP I/O Bottom plate ground. See pin 43 description.
VDDB
O
Internal regulated voltage used for the internal control circuitry. Place a 0.22µF, X5R/X7R,
capacitor between this pin and BGND.
BGND G Ground for VDDB. See pin 45 description.
Digital synchronization input. This pin accepts either an input clock to phase lock the
S_IN I internal switching frequency or a S_OUT signal from another EN2340QI. Leave this pin
floating if not used.
S_OUT
O
Digital synchronization output. PWM signal is output on this pin. Leave this pin floating if
not used.
Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power
POK O system state indication. POK is logic high when VOUT is within -10% of VOUT nominal.
Leave this pin floating if not used.
Output enable. Applying a logic high to this pin enables the output and initiates a soft-start.
ENABLE
I
Applying a logic low disables the output. ENABLE logic cannot be higher than AVIN (refer to
Absolute Maximum Ratings). Do not leave floating. See Power Up/Down Sequencing
section for details.
AVIN
P
3.3V Input power supply for the controller. Place a 1µF, X5R/X7R, capacitor between AVIN
and AGND.
AGND
G
Analog ground. This is the ground return for the controller. All AGND pins need to be
connected to a quiet ground.
External feedback input. The feedback loop is closed through this pin. A voltage divider at
VFB I/O VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A
phase lead network from this pin to VOUT is also required to stabilize the loop.
EAOUT O Optional error amplifier output. Allows for customization of the control loop.
SS
I/O
Soft-start node. The soft-start capacitor is connected between this pin and AGND. The
value of this capacitor determines the startup time.
Programmable over-current protection. Placement of a resistor on this pin will adjust the
RCLX
I/O
over-current protection threshold. See Table 2 for the recommended RCLX Value to set
OCP at the nominal value specified in the Electrical Characteristics table. No current limit
protection when this pin is left floating.
FADJ
Adding a resistor (R_FS) to this pin will adjust the switching frequency of the EN2340QI. See
I/O Table 1 for suggested resistor values on R_FS for various PVIN/VOUT combinations to
maximize efficiency. Do not leave floating.
PGND
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes.
06878
October 9, 2013
www.altera.com/enpirion, Page 3
Rev E