EN2340QI Datasheet, PDF (11/23 Pages) Enpirion, Inc. – 204A Voltage Mode Synchronous Buck PWM

Power Up Sequence
The EN2340QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN. The
EN2340QI is not “hot pluggable.” Refer to the PVIN
Slew Rate specification on page 4.
Single Input Supply Application (PVIN):
V_IN
22µF
1206
RVB
4.75k
1µF
22nF
0.22µF
RPG
560
10k
4.02k
1µF
PG BTMP VDDB BGND
PVIN
VOUT
EN2340QI
ENABLE
AVINO
AVIN
SS
VFB
47nF
PGND
FADJ
AGND
PGND
RCLX
V_OUT
2x
22µF R_A
0805
CA
RCA
RB
RFS
RCLX
Figure 5: Single Input Supply Schematic
The EN2340QI has an internal linear regulator that
converts PVIN to 3.3V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN on the EN2340QI. In this application, the
following external components are required: Place
a 1µF, X5R/X7R capacitor between AVINO and
AGND as close as possible to AVINO. Place a
1µF, X5R/X7R capacitor between AVIN and AGND
as close as possible to AVIN. In addition, place a
resistor (R_VB) between VDDB and AVIN, as shown
in Figure 5. Altera recommends R_VB=4.75kΩ. In this
application, ENABLE cannot be asserted before
PVIN. See diagram below for a recommended
startup and shutdown sequencing.
PVIN
12V
PVIN slew rate limitations
as per datasheet
0V
3.3V
ENABLE _0V
Delay from ENABLE rising
edge to soft start begin
~ 1ms
VOUT
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Start Time ≈ 2ms
w/Css=47nF
PVIN – Recommended
to be ramped down
after the Vout soft-
shutdown occurs
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
Figure 6: Single Supply Startup/Shutdown Sequence
If no external enable signal is used, a resister
divider (see Figure 5) from PVIN to ENABLE and
then to ground can be used to enable and disable
EN2340QI
the device at a programmed PVIN voltage level.
The lower resistor (4.02k) can be adjusted to set
startup and shutdown at a specific PVIN voltage
level. See ENABLE and DISABLE thresholds in the
Electrical Characteristics table.
Dual Input Supply Application (PVIN and AVIN):
V_IN
22µF
1206
RPG
560
V_AVIN
1µF
47nF
22nF
0.22µF
PG BTMP VDDB BGND
PVIN
VOUT
EN2340QI
ENABLE
AVINO
AVIN
SS
VFB
V_OUT
2x
22µF R_A
CA
0805
RCA
PGND
PGND
FADJ AGND RCLX
RB
RFS
RCLX
Figure 7: Dual Input Supply Schematic
In this application, place a 1µF, X5R/X7R, capacitor
between AVIN and AGND as close as possible to
AVIN. Refer to Figure 7 for a recommended
schematic for a dual input supply application.
For dual input supply applications, the sequencing
of the two input supplies, PVIN and AVIN, is very
important. There are two common acceptable turn-
on sequences for the device. AVIN can always
come up before PVIN. If PVIN comes up before
AVIN, then ENABLE must be toggled last, after
AVIN is asserted. Do not turn off AVIN before PVIN
and ENABLE during shutdown. Doing so will
disable the internal controller while there may still
be energy in the system. The device will not soft-
shutdown properly and damage may occur. See
diagram below for a recommended startup and
shutdown sequencing.
PVIN
12V
PVIN slew rate limitations
as per datasheet
0V
PVIN powered
down before AVIN
3.3V
AVIN
AVIN powered up before PVIN
0V
3.3V
ENABLE _0V
Delay from ENABLE rising
edge to soft start begin
~ 1ms
VOUT
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Start Time ≈ 2ms
w/Css=47nF
PVIN/AVIN –
Recommended
to be ramped down
after the Vout soft-
shutdown occurs
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
Figure 8: Dual Supply Startup/Shutdown Sequencing
www.altera.com/enpirion, Page 11
06878
October 9, 2013
Rev E