EN2340QI Datasheet, PDF (12/23 Pages) Enpirion, Inc. – 204A Voltage Mode Synchronous Buck PWM

Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft-start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Time (8ms) in order for the device to be re-
enabled. To ensure accurate startup sequencing
the ENABLE/DISABLE signal should be faster than
1V/100µs. A slower ENABLE/DISABLE signal may
result in a delayed startup and shutdown response.
Pre-Bias Precaution
The EN2340QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN2340QI is not pre-biased when the EN2340QI is
first enabled.
Frequency Synchronization
The switching frequency of the EN2340QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2340QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the presence of
an external clock signal and automatically phase-
locks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.8MHz to 1.8MHz. The
external clock frequency must be within ±10% of
the nominal switching frequency set by the R_FS
resistor. It is recommended to use a synchronized
clock frequency close to the typical frequency
recommendations in Table 1. A 3.01kΩ resistor
from FQADJ to ground is recommended for clock
frequencies within ±10% of 1MHz. When no clock
is present, the device reverts to the free running
frequency of the internal oscillator set by the R_FS
resistor.
The efficiency performance of the EN2340QI for
various PVIN/VOUT combinations can be optimized
by adjusting the switching frequency. Table 1
shows recommended R_FS values for various
PVIN/VOUT combinations in order to optimize
performance of the EN2340QI.
EN2340QI
1.800
Rfs vs. SW Frequency
1.600
1.400
1.200
1.000
0.800
CONDITIONS
V_IN = 6V to 12V
V_OUT = 0.8V to 3.3V
0.600
0 2 4 6 8 10 12 14 16 18 20 22
R_FS RESISTOR VALUE (kΩ)
Figure 9. Typical R_FS vs. Switching Frequency
PVIN VOUT
R_FS
5.0V
30k
Typical fsw
1.7 MHz
3.3V
15k
12V
2.5V
1.8V
10k
4.87k
1.38 MHz
1.3 MHz
1.15 MHz
1.2V
<1.0V
2.5V
1.65k
1.3k
22.1k
0.95 MHz
0.8 MHz
1.4 MHz
1.8V
10k
5V
1.5V
6.65k
1.2V
4.87k
1.3 MHz
1.25 MHz
1.15 MHz
<1.0V 3.01k
1.0 MHz
Table 1: Recommended R_FS Values
Spread Spectrum Mode
The external clock frequency may be swept
between 0.8MHz and 1.8MHz at repetition rates of
up to 10 kHz in order to reduce EMI frequency
components.
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin (pin
56) and the AGND pin (pin 52). During start-up of
the converter, the reference voltage to the error
amplifier is linearly increased to its final level by an
internal current source of approximately 10µA. The
soft-start time is measured from when V_IN > V_UVLOR
and ENABLE pin voltage crosses its logic high
threshold to when V_OUT reaches its programmed
value. The total soft-start time can be calculated by:
Soft Start Time (ms): T_SS ≈ C_ss [nF] x 0.067
www.altera.com/enpirion, Page 12
06878
October 9, 2013
Rev E