EN2340QI Datasheet, PDF (13/23 Pages) Enpirion, Inc. – 204A Voltage Mode Synchronous Buck PWM

Typical soft-start time is approximately 3.2ms with
SS capacitor value of 47nF.
POK Operation
The POK signal is an open drain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Over-Current Protection (OCP)
The current limit function is achieved by sensing
the current flowing through a sense PFET. When
the sensed current exceeds the current limit for
more than 32 cycles, both power FETs are turned
off for the rest of the switching cycle. If the over-
current condition is removed, the over-current
protection circuit will re-enable PWM operation. In
the event the OCP circuit trips consistently in
normal operation, the device enters a hiccup mode.
While in hiccup mode, the device is disabled for a
short while and restarted with a normal soft-start.
The hiccup time is approximately 32ms. This cycle
can continue indefinitely as long as the over current
condition persists. The OCP trip point depends on
PVIN, VOUT and the RCLX resistor.
Generally, the higher the RCLX value, the higher
the current limit threshold for a given input and
output voltage condition.
Note: If the RCLX pin is left open, the output
current will be unlimited and the device will not
have current limit protection.
Reference Table 2 for a list of recommended
resistor values on RCLX that will set the OCP trip
point at the typical value of 6A, also specified in the
Electrical Characteristics table. Contact
www.altera.com/mysupport for specific RCLX
values to be use for special cases.
EN2340QI
44
42
40
38
36
34
32
30
28
26
0.5
Recommended R_CLX Value
PVIN = 12V
PVIN = 8V
PVIN = 5V
CONDITIONS
Current Limit ≈ 6A
T_A = 25 C
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
OUTPUT VOLTAGE (V)
Figure 10. Typical R_CLX vs. Output Voltage
PVIN
V_OUT Range
0.75V < V_OUT ≤ 1.2V
5V 1.2V < VOUT ≤ 2.0V
2.0V < V_OUT ≤ 2.5V
0.75V < V_OUT ≤ 1.2V
1.2V < V_OUT ≤ 2.0V
8V 2.0V < V_OUT ≤ 3.0V
3.0V < V_OUT ≤ 4.0V
4.0V < V_OUT ≤ 5.0V
0.75V < V_OUT ≤ 1.2V
12V
1.2V < V_OUT ≤ 2.0V
2.0V < V_OUT ≤ 3.0V
3.0V < V_OUT ≤ 4.0V
4.0V < V_OUT ≤ 5.0V
R_CLX
Value
30.1kΩ
31.6kΩ
33.2kΩ
30.9kΩ
32.4kΩ
35.7kΩ
38.3kΩ
40.2kΩ
31.6kΩ
33.2kΩ
36.5kΩ
39.2kΩ
41.2kΩ
Curre nt
Limit
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
Table 2: Recommended R_CLX Values and Current Limit
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the junction temperature exceeds
approximately 160°C. After a thermal shutdown
event, when the junction temperature drops by
approx 35°C, the converter will re-start with a
normal soft-start.
Input Under-Voltage Lock-Out (UVLO)
Internal circuits ensure that the converter will not
start switching until the AVIN input voltage is above
the specified minimum voltage. Hysteresis, input
de-glitch and output leading edge blanking ensures
high noise immunity and prevents false UVLO
triggers.
06878
October 9, 2013
www.altera.com/enpirion, Page 13
Rev E