AK8856 Datasheet, PDF (95/105 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

ASAHI KASEI
[ AK8856 ]
YC Delay Control Register (R/W) [Sub Address 0x0B]
YC Delay Control Register Definition
Sub Address 0x0B
bit 7
bit 6
Reserved
Reserved
0
0
bit 5
Reserved
0
bit 4
bit 3
Reserved
Reserved
Default Value
0
0
bit 2
YCDELAY2
Default Value : 0x00
bit 1
bit 0
YCDELAY1 YCDELAY0
0
0
0
YC Delay Control Register Definition
BIT Register Name
bit 0 YCDELAY0
~
~
Y/C Delay Control
bit 2 YCDELAY2
bit 3
~
Reserved
Reserved bit
bit 7
R/W
Definition
Adjusts amount of Y/C output delay; Delay amount
depends on the selected output mode.
VGA/QVGA/QVGA Rotated/CIF Rotated :
12.2727MHz clock cycles per each one delay
(81.5ns)
601/CIF/QCIF : 13.5MHz sample clock cycles per
each one delay ( 74 ns)
R/W ^{YCDELAY2 : YCDELAY0}
101 : Y is delayed from C by 3 clock cycles
110 : Y is delayed from C by 2 clock cycles
111 : Y is delayed from C by 1 clock cycles
000 : no delay between Y and C
001 : Y is advanced from C by 1 clock cycles
010 : Y is advanced from C by 2 clock cycles
011 : Y is advanced from C by 3 clock cycles
R/W Reserved
Rev-01
95
2007/03