AK8856 Datasheet, PDF (29/105 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

ASAHI KASEI
[ AK8856 ]
Sync-Separation, Sync-Detection
Sync-Detection and Separation are executed from the digitized input signal. The recognized Sync-signal is used
as reference timing for decoding process.
Digital Pedestal Clamp
The pedestal is clamped in the digital domain. The internal clamp level differs according to the type of input
signal (286mV Sync signal or 300 mV Sync signal), but the output is fixes the pedestal position at code 16 (8-bit
Rec. 601 level) for either condition.
YC Separation
YC separation can be either 1D or 2D. The filter characteristic for YC separation is shown here (27 MHz
sampling):
10
0
-10 ^{0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5}
-20
-30
-40
-50
frequency[MHz]
YC separation is set by the YCSEP-bit of the Control 1 Register (R/W) [Sub Address 0x03]
Sub Address 0x03
bit 7
bit 6
Reserved
VDFLD
0
0
bit 5
AGCTR
0
bit 4
bit 3
AGCC1
AGCC0
Default Value
0
0
bit 2
CKILSEL1
Default Value: 0x00
bit 1
bit 0
CKILSEL0
YCSEP
0
0
0
YCSEP-bit setting results in the following conditions:
YCSEP-bit
QVGA, QCIF, QVGAL, CIFL
NTSC
CIF
Y: 1DYC-filter
0
C: 1DYC-filter
Y: 1DYC-filter
AK8855 compatible
C: 1DYC-filter
1
Y: 1DYC-filter
C: 2DYC-filter
AK8855 compatible
VGA, 601
Y: 1DYC-filter
C: 1DYC-filter
AK8855 compatible
Y : 2DYC-filter
C : 2DYC-filter
PAL
DPAL* switch is turned ON / OFF by the YCSEP-bit (DPAL switch is always OFF in VGA mode (YCSEP-bit has
no effect )).
DPAL*: process of averaging Color phases between Lines.
Rev-01
29
2007/03