AK8856 Datasheet, PDF (6/105 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

ASAHI KASEI
[ AK8856 ]
Pin Description
AK8856VG
Pin
Pin
Name
A6 XTI
B7 XTO
B4 CLKMOD
D7 OE
E6 SDA
D6 SCL
C6 RSTN
B6 PDN
F7 DTCLK
F3 DATA7
G3 DATA6
F4 DATA5
G4 DATA4
A/D/P I/O
Functional Outline
Quartz crystal oscillator connection (tie to digital ground via a 22pF capacitor)
D
I - 27.00 MHz crystal oscillator should be used
- input from 27.00 MHz crystal oscillator is connected to this pin
Quartz crystal oscillator connection (tie to digital ground via a 22pF capacitor)
- 27.00 MHz crystal oscillator should be used.
D
O - this pin outputs DVSS level when PDN = L.
- when a crystal oscillator is not used, this pin can either be left open (NC) or
connected to DVSS
Clock mode set: connect to either DVDD (high) or DVSS (low)
D
I - Low setting: crystal oscillator is used
- High setting: external clock source is used
Output enable
P
I ^{- L : digital output pins are at high-Z}
- H : data is available for output
- Hi-Z input on OE pin is prohibited
I²C data
P
I/O
- this pin is pulled-up to PVDD
- Hi-Z input is allowed when PDN is low
- SDA input is not accepted during reset operation
I²C clock input
P
I
- an input level below PVDD should be input
- Hi-Z input is allowed when PDN is low
- SCL input is not accepted during reset operation
Reset signal input
- Hi-Z input to this pin is prohibited
P
I _{- L: reset}
- H: normal operation
Power-down control
P
I
- Hi-Z input to this pin is prohibited
- L: power-down
- H: normal operation
Data clock for output interface
P
I/O ^{- output state is separately controlled by combinations of RSTN/PDN/OE pin}
settings (note 1)
- this pin is used as an I/O pin in test mode
Data output (MSB)
P
I/O - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1)
- this pin is used as an I/O pin in test mode
P
O
Data output
- output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1)
Data output
P
I/O - output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1)
- this pin is used as an I/O pin in test mode
P
O
Data output pin
- output state is controlled by combinations of RSTN/PDN/OE pin settings (note 1)
Rev-01
6
2007/03