AK8856 Datasheet, PDF (27/105 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

ASAHI KASEI
[ AK8856 ]
Clock
Sampling is controlled by a fixed clock in the AK8856. A PLL to synchronize the sampling clock with analog input
signal is not built-in. The clock rate differs depending on the selected output picture sizes and types of input
signal. The internal operating clock is either 27MHz or 24.5454MHz, which is generated from the input clock by
the PLL. The internal clock rate is automatically determined by the output picture size.
VGA
QVGA
CIF
QCIF
601
QVGA
CIF
Operation clock
24.5454MHz
24.5454MHz
27MHz
27MHz
27MHz
27MHz
24.5454MHz
24.5454MHz
Size
640 x 480
320 x 240
352 x 288
176 x 144
720 x 480
720 x 576
240 x 180
288 x 216
Signal
NTSC/PAL
NTSC/PAL
NTSC/PAL
NTSC/PAL
NTSC
PAL
NTSC/PAL
NTSC/PAL
Note
Interlace output
Progressive output
Rotated size
Rotated size
note) For rotated CIF size, both the left-end and right-end 16 pixels are omitted and 288 X 216 picture size is output (90% area of the
effective picture is output). When decoding CIF (NTSC), output rate is 2X speed of input HD.
Output Picture Size
The output picture size is set by the [OFORM2 : OFORM0] bits of Output Control 1 Register (R/W) [Sub Address 0x01].
[OFORM2:OFORM0]-bit
[OFORM2:OFROM0]-bit
000
001
010
011
100
101
110
Function
QVGA
VGA
CIF
QCIF
Rotated QVGA
Rotated CIF
601
Condition
Rev-01
27
2007/03