AK4645EN Datasheet, PDF (93/96 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4645]
„ ΫϩοΫͷఀࢭ
ADC͓ΑͼDACΛ࢖༻͠ͳ͍৔߹͸ɺϚελΫϩοΫΛఀࢭ͢Δ͜ͱ͕Ͱ͖·͢ɻ
1. PLLϚελϞʔυͷ৔߹
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
"1" or "0"
Input
(1)
(2)
(3)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 8kHz
(1) (2) Addr:01H, Data:08H
(3) Stop an external MCKI
Figure 83. Clock Stopping Sequence (1)
<खॱྫ>
(1) PLLͷύϫʔμ΢ϯ: PMPLL bit = “1” → “0”
(2) MCKOग़ྗͷఀࢭ: MCKO bit = “1” → “0”
(3) ֎෦ΫϩοΫΛࢭΊͯԼ͍͞ɻ
2. PLLϚελϞʔυͷ৔߹PLLεϨʔϒϞʔυ(LRCK, BICK pin)ͷ৔߹
PMPLL bit
(Addr:01H, D0)
External BICK
External LRCK
Input
Input
(1)
(2)
(2)
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 84. Clock Stopping Sequence (2)
<खॱྫ>
(1) PLLͷύϫʔμ΢ϯ: PMPLL bit = “1” → “0”
(2) ֎෦ΫϩοΫΛࢭΊͯԼ͍͞ɻ
3. PLLεϨʔϒϞʔυ(MCKI pin)ͷ৔߹
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
Input
(1)
(1)
(2)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 85. Clock Stopping Sequence (3)
<खॱྫ>
(1) PLLͷύϫʔμ΢ϯ: PMPLL bit = “1” → “0”
MCKOग़ྗͷఀࢭ: MCKO bit = “1” → “0”
(2) ֎෦ΫϩοΫΛࢭΊͯԼ͍͞ɻ
MS0543-J-00
- 93 -
2006/09