AK4645EN Datasheet, PDF (13/96 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4645]
DCಛੑ

(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V)
Parameter
Symbol
min
typ
High-Level Input Voltage 2.2V≤TVDD≤3.6V VIH 70%TVDD
-
1.6V≤TVDD<2.2V VIH 75%TVDD
-
Low-Level Input Voltage
2.2V≤TVDD≤3.6V VIL
-
-
1.6V≤TVDD<2.2V VIL
-
-
High-Level Output Voltage
(Iout=−200µA) VOH TVDD−0.2
-
Low-Level Output Voltage
(Except SDA pin: Iout=200µA) VOL
-
-
(SDA pin: Iout=3mA) VOL
-
-
Input Leakage Current
Iin
-
-
max
-
-
30%TVDD
25%TVDD
-
Units
V
V
V
V
V
0.2
V
0.4
V
±10
µA
εΠονϯάಛੑ
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; C_L=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
Pulse Width Low
tCLKL 0.4/fCLK
-
Pulse Width High
tCLKH 0.4/fCLK
-
MCKO Output Timing
Frequency
fMCK
0.2352
-
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
27
-
-
12.288
60
-
MHz
ns
ns
MHz
%
%
LRCK Output Timing
Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Output Timing
Period
BCKO bit = “0”
BCKO bit = “1”
Duty Cycle
fs
7.35
tLRCKH
-
Duty
-
tBCK
-
tBCK
-
dBCK
-
-
tBCK
50
1/(32fs)
1/(64fs)
50
48
kHz
-
ns
-
%
-
ns
-
ns
-
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
MCKO Output Timing
Frequency
fMCK
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
256fs at fs=32kHz, 29.4kHz
dMCK
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
11.2896
0.4/fCLK
0.4/fCLK
0.2352
40
-
7.35
tBCK−60
45
1/(64fs)
0.4 x tBCK
0.4 x tBCK
-
27
MHz
-
-
ns
-
-
ns
-
12.288
MHz
50
60
%
33
-
%
-
48
kHz
-
1/fs − tBCK ns
-
55
%
-
1/(32fs)
ns
-
-
ns
-
-
ns
MS0543-J-00
- 13 -
2006/09