AK4645EN Datasheet, PDF (26/96 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4645]
ج४ΫϩοΫ͕LRCK or BICKΑΓೖྗͷ৔߹͸ɺFS3, FS1-0 bitsͰαϯϓϦϯάप೾਺ͷઃఆΛߦͬͯԼ͞
͍(Table 7)ɻ
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range
0
0
Don’t care
0
0
7.35kHz ≤ fs ≤ 8kHz Default
1
0
Don’t care
0
1
8kHz < fs ≤ 12kHz
2
0
Don’t care
1
0
12kHz < fs ≤ 16kHz
3
0
Don’t care
1
1
16kHz < fs ≤ 24kHz
6
1
Don’t care
1
0
24kHz < fs ≤ 32kHz
7
1
Don’t care
1
1
32kHz < fs ≤ 48kHz
Others
Others
N/A
Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
„ PLLͷΞϯϩοΫʹ͍ͭͯ
1) PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”)
͜ͷϞʔυͰ PMPLL bit = “0” Æ “1”ޙͨ͠ʹPLL͕ϩοΫ͢Δ·ͰͷؒɺBICKͱLRCK͸ “L”Λग़ྗɺMCKO
bit = “1”ͷͱ͖MCKO pin͔Β͸ਖ਼ৗͰͳ͍प೾਺ͷΫϩοΫ͕ग़ྗ͞Ε·͢ɻMCKO bit = “0”ͷ৔߹͸ɺ
MCKO pin͸ “L”Λग़ྗ͠·͢ɻ(See Table 8)
PLLϩοΫޙɺBICKͱLRCKग़ྗ͸ “L”͔ΒΫϩοΫग़ྗͱͳΓ·͢ɻ࠷ॳͷ1पظ෼ͷLRCK, BICK͸ɺਖ਼
ৗͰͳ͍Մೳੑ͕͋Γ·͕͢ɺ1fsʹޙ͸ਖ਼ৗͳΫϩοΫʹͳΓ·͢ɻ
αϯϓϦϯάप೾਺Λมߋ͢Δ৔߹͸Ұ౓PMPLL bit = “0”ʹ͢Δ͜ͱͰΞϯϩοΫঢ়ଶͷෆఆͳBICK,
LRCKΛग़ྗͤͣ͞ʹ “L”Λग़ྗͤ͞Δ͜ͱ͕Ͱ͖·͢ɻ
PLL State
PMPLL bit “0” Æ “1”௚ޙ
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
ෆఆ
BICK pin
“L” Output
LRCK pin
“L” Output
PLL Unlock ࣌(ه্Ҏ֎)
“L” Output
ෆఆ
ෆఆ
ෆఆ
PLL Lock ࣌
“L” Output
See Table 10
See Table 11
1fs Output
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
͜ͷϞʔυͰ͸ PMPLL bit = “0” Æ “1”ޙͨ͠ʹPLL͕ϩοΫ͢Δ·ͰͷؒɺMCKO͔Β͸ਖ਼ৗͰͳ͍प೾਺
ͷΫϩοΫ͕ग़ྗ͞Ε·͢ɻͦͷޙɺPLL͕ϩοΫ͢ΔͱMCKO pin͔ΒTable 10Ͱબ୒͞ΕͨΫϩοΫ͕ग़
ྗ͞Ε·͢ɻୠ͠ɺPLL͕ΞϯϩοΫʹͳͬͨ৔߹ɺADCͼٴDAC͔Β͸ਖ਼ৗͳσʔλ͕ग़ྗ͞Ε·ͤΜɻ
DACʹؔͯ͠͸ɺDACL, DACH bitsΛ “0”ʹ͢Δ͜ͱʹΑΓग़ྗΛϛϡʔτ͢Δ͜ͱ͕ՄೳͰ͢ɻ
PLL State
PMPLL bit “0” Æ “1”௚ޙ
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
ෆఆ
PLL Unlock ࣌(ه্Ҏ֎)
“L” Output
ෆఆ
PLL Lock ࣌
“L” Output
Output
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MS0543-J-00
- 26 -
2006/09