AK4645EN Datasheet, PDF (24/96 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4645]
ػೳઆ໌
„ γεςϜΫϩοΫ
֎෦ͱͷI/FϞʔυ͸ҎԼͷ4௨Γͷํ๏͕͋Γ·͢ɻ(See Table 2 and Table 3.)
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 38)
1
1
See Table 5
Figure 19
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1
0
See Table 5
Figure 20
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
1
0
See Table 5
Figure 21
Figure 22
EXT Slave Mode
0
0
x
Figure 23
EXT Master Mode
0
1
x
Figure 24
Note 38. PLL Master Modeʹઃఆ͢ΔաఔͰɺM/S bit = “1”, PMPLL bit = “0”, MCKO bit = “1”ͷͱ͖MCKO pin
͔Βਖ਼ৗͰͳ͍प೾਺ͷΫϩοΫ͕ग़ྗ͞Ε·͢ɻ
Table 2. Clock Mode Setting (x: Don’t care)
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
MCKO bit
0
1
0
1
MCKO pin
“L”
PS1-0 bits
Ͱબ୒
“L”
PS1-0 bits
Ͱબ୒
MCKI pin
PLL3-0 bits
Ͱબ୒
PLL3-0 bits
Ͱબ୒
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
“L”
GND
EXT Slave Mode
FS1-0 bits
0
“L”
Ͱબ୒
EXT Master Mode
FS1-0 bits
0
“L”
Ͱબ୒
Table 3. Clock pins state in Clock Mode
BICK pin
Output
(BCKO bit
Ͱબ୒)
Input
(≥ 32fs)
Input
(PLL3-0
bitsͰબ୒)
Input
(≥ 32fs)
Output
(BCKO bit
Ͱબ୒)
LRCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
„ ϚελϞʔυͱεϨʔϒϞʔυͷ੾Γସ͑
ϚελϞʔυͱεϨʔϒϞʔυͷ੾Γସ͑͸M/S bitͰߦ͍·͢ɻ“1”ͰϚελϞʔυɺ“0”ͰεϨʔϒϞʔυ
Ͱ͢ɻAK4645͸ύϫʔμ΢ϯ࣌ (PDN pin = “L”)ɺͼٴύϫʔμ΢ϯղআޙ͸εϨʔϒϞʔυͰ͢ɻύϫʔ
μ΢ϯղআޙɺM/S bitΛ “1”ʹมߋ͢Δ͜ͱͰϚελϞʔυʹͳΓ·͢ɻ
ϚελϞʔυͰ࢖༻͢Δ৔߹ɺM/S bitʹ “1”͕ॻ͖ࠐ·ΕΔ·ͰɺAK4645ͷLRCK, BICK pin͸ϑϩʔςΟϯ
άͷঢ়ଶͰ͢ɻͦͷͨΊɺAK4645ͷLRCK, BICK pinʹ100kΩఔ౓ͷϓϧΞοϓ͋Δ͍͸ϓϧμ΢ϯ఍߅Λೖ
ΕΔඞཁ͕͋Γ·͢ɻ
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 4. Select Master/Slave Mode
Default
MS0543-J-00
- 24 -
2006/09