AK8181F Datasheet, PDF (9/12 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
AK8181F
Table 1: Control Input Function Table
Inputs
Outputs
OE
CLK_EN
CLK_SEL Selected Source
Q0:Q3
Q0n:Q3n
1
0
0 (Open)
PCLK0p/n
Disabled: Low
Disabled: High
1
0
1
PCLK1p/n
Disabled: Low
Disabled: High
1
1 (Open)
0 (Open)
PCLK0p/n
Enabled
Enabled
1
1 (Open)
1
PCLK1p/n
Enabled
Enabled
0
X
X
---
Hi-Z
Hi-Z
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 13. In the active mode, the state of the outputs are a function of the PCLK0p/n and PCLK1p/n
as described in Table 2.
Figure 13 CLK_EN Timing Diagram
Inputs
PCLK0/1p
0
1
0
1
Biased ⁽¹⁾
Biased ⁽¹⁾
PCLK0/1n
1
0
Biased ⁽¹⁾
Biased ⁽¹⁾
0
1
Table 2 Clock Input Function Table
Outputs
Q0:Q3
Q0n:Q3n
Input to Output
Low
High
Differential to Differential
High
Low
Differential to Differential
Low
High
Single Ended to Differential
High
Low
Single Ended to Differential
High
Low
Single Ended to Differential
Low
High
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
(1) Please refer to the application Information section, “Wiring the Differential Input to Accept Single Ended
Levels”.
draft-E-02
-9-
Dec-2012