AK8181F Datasheet, PDF (5/12 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

DC Characteristics (LVCMOS/LVTTL)
All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted
AK8181F
Parameter
Symbol
Conditions
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VIL
CLK_SEL
Vin=VDD=3.465V
CLK_EN, OE
IH
Vin=VDD=3.465V
Vin=VSS,
CLK_SEL
VDD=3.465V
IL
Vin=VSS,
CLK_EN, OE
VDD=3.465V
MIN
2.0
-0.3
-5
-150
TYP
MAX Unit
VDD+0.3 V
0.8
V
150 μA
5
μA
μA
μA
DC Characteristics (Differential)
All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol Conditions
MIN
TYP
MAX Unit
Input High Current
PCLK0p
PCLK0n
Vin=VDD=3.465V
IH
Vin=VDD=3.465V
150
μA
5
μA
Vin=VSS,
PCLK0p
-5
μA
VDD=3.465V
Input Low Current
IL
Vin=VSS,
PCLK0n
-150
μA
VDD=3.465V
Peak-to-Peak Input Voltage
VPP
0.15
1.3
V
Common Mode Input Voltage ^{(1) (2)}
VCMR
VSS+0.5
VDD-0.85 V
(1) For single ended applications, the maximum input voltage for PCLK0p and PCLK0n is VDD+0.3V.
(2) Common mode voltage is defined as VIH.
DC Characteristics (LVPECL)
All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol Conditions
MIN
TYP
Input High Current
PCLK1p
PCLK1n
Vin=VDD=3.465V
IH
Vin=VDD=3.465V
Input Low Current
PCLK1p
PCLK1n
Vin=VSS,
VDD=3.465V
IL
Vin=VSS,
VDD=3.465V
-5
-150
Peak-to-Peak Input Voltage
VPP
0.3
Common Mode Input Voltage ^{(1) (2)}
VCMR
VSS+1.5
(1) For single ended applications, the maximum input voltage for PCLK1p and PCLK1n is VDD+0.3V.
(2) Common mode voltage is defined as VIH.
MAX
150
5
1.0
VDD
Unit
μA
μA
μA
μA
V
V
draft-E-02
-5-
Dec-2012