AK8181F Datasheet, PDF (10/12 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

AK8181F
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure.8 shows how the differential input can be wired to accept single ended levels. The reference
voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be
located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position
the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and
VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
Figure 14 Single Ended Signal Driving Differential Input
Dec-2012
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draft-E-02