AK8181F Datasheet, PDF (6/12 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

AK8181F
DC Characteristics (LVDS)
All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
High Impedance Leakage Current
Differential Output Short Circuit Current
Output Voltage High
Output Voltage Low
VOD
ΔVOD
VOS
ΔVOS
IOZ
IOSD
VOH
VOL
OE=L
MIN
TYP
200
280
0
1.125 1.25
5
-10
-3.5
1.34
0.9
1.06
MAX Unit
360
mV
40
mV
1.375
V
25
mV
+10
μA
-5
mA
1.6
V
V
AC Characteristics
All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN TYP MAX Unit
Output Frequency
fOUT
650 MHz
Propagation Delay ⁽¹⁾
Output Skew ^{(2) (3)}
Part-to-Part Skew ^{(3) (4)}
Output Rise/Fall Time ⁽⁵⁾
tPD
0.9
tsk(O)
tskPP
tr, tf
20% to 80% @50MHz
100
2.5 ns
30 ps
600 ps
300 ps
Output Duty Cycle
DCOUT
45
50
55 %
All parameters measured at f ≤ 650MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
(1) Measured from the differential input crossing point to the differential output crossing point.
(2) Defined as skew between outputs at the same supply voltage and with equal load conditions.
(3) This parameter is defined in accordance with JEDEC Standard 65.
(4) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
(5) Design value.
Dec-2012
draft-E-02
-6-