AK8181F Datasheet, PDF (1/12 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

AK8181F
3.3V LVDS 1:4
Preliminary Clock Fanout Buffer
AK8181F
Features
Four differential 3.3V LVDS outputs
Selectable differential PCLK0p/n or LVPECL
clock inputs
PCLK0p/n pair can accept the following
differential input levels; LVDS, LVPECL,
LVHSTL, SSTL, HCSL
PCLK1p/n supports the following input types;
LVPECL, CML, SSTL
Clock output frequency up to 650MHz
Translates any single-ended input signal to
3.3V LVDS levels with resistor bias on
PCLK0n input
Output skew : 30ps (maximum)
Part-to-part skew : 600ps (maximum)
Propagation delay : 2.5ns (maximum)
Operating Temperature Range: -40 to +85℃
Package: 20-pin TSSOP (Pb free)
Pin compatible with ICS8543I
Description
The AK8181F is a member of AKM’s LVDS clock
fanout buffer family designed for telecom,
networking and computer applications, requiring a
range of clocks with high performance and low
skew. The AK8181F distributes 4 buffered clocks.
AK8181F are derived from AKM’s long-term-
experienced clock device technology, and enable
clock output to perform low skew. The AK8181F is
available in a 20-pin TSSOP package.
Block Diagram
draft-E-02
-1-
Dec-2012