AK8181F Datasheet, PDF (2/12 Pages) Asahi Kasei Microsystems – 3.3V LVDS 1:4 Clock Fanout Buffer

AK8181F
Pin Descriptions
Package: 20-Pin TSSOP(Top View)
Pin No.
1
2
3
4
5
6
7
8
9
10
Pin Name
VSS
CLK_EN
CLK_SEL
PCLK0p
PCLK0n
PCLK1p
PCLK1n
OE
VSS
VDD
Pin
Type
PWR
IN
IN
IN
IN
IN
IN
IN
PWR
PWR
Pullup
down
---
Pull up
Pull down
Pull down
Pull up
Pull down
Pull up
Pull up
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Description
Negative power supply
Synchronizing clock output enable (LVCMOS/LVTTL)
Pin is connected to VDD by internal resistor. (typ. 51kΩ
High (Open): clock outputs follow clock input.
Low: Q outputs are forced low, Qn outputs are forced high.
CLK Select Input (LVCMOS/LVTTL)
Pin is connected to VSS by internal resistor. (typ. 51kΩ
High: selects PCLK1p/n inputs
Low (Open): selects PCLK0p/n inputs
Non-inverting differential clock input
Pin is connected to VSS by internal resistor. (typ. 51kΩ
*When using PCLK1 input (CLK_SEL=High), it should be
connected to VSS or opened.
Inverting differential clock input
Pin is connected to VDD by internal resistor. (typ. 51kΩ
*When using PCLK1 input (CLK_SEL=High), it should be
connected to VDD or opened.
Non-inverting differential LVPECL clock input
Pin is connected to VSS by internal resistor. (typ. 51kΩ
*When using PCLK0 input (CLK_SEL=Low), it should be
connected to VSS or opened.
Inverting differential LVPECL clock input
Pin is connected to VDD by internal resistor. (typ. 51kΩ
*When using PCLK0 input (CLK_SEL=Low), it should be
connected to VDD or opened.
Output enable. Controls enabling and disabling of outputs Q0,
Q0n through Q3, Q3n
Pin is connected to VDD by internal resistor. (typ. 51kΩ)
Negative power supply
Positive power supply
Dec-2012
draft-E-02
-2-