AK5356 Datasheet, PDF (9/22 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT ADC WITH MIC AMP & PGA

ASAHI KASEI
[AK5356]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=2.0 ∼ 3.3V, DVDD=1.8 ∼ 3.3V; C_L=20pF)
Parameter
Symbol
min
Master Clock Timing (MCLK)
256fs: Frequency
fCLK
2.048
Pulse Width Low
tCLKL
28
Pulse Width High
tCLKH
28
384fs: Frequency
fCLK
3.072
Pulse Width Low
tCLKL
23
Pulse Width High
tCLKH
23
LRCK Timing
Frequency
fs
8
Duty Cycle
Duty
45
Serial Interface Timing
BCLK Period
tBLK
312.5
BCLK Pulse Width Low
tBLKL
130
Pulse Width High
tBLKH
130
BCLK “↓” to LRCK edge
tBLR -tBLKH+50
LRCK to SDTO (MSB) (Note 19)
tDLR
BCLK “↓” to SDTO
tDSS
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSS
50
tCSH
50
Power-down & Reset Timing
PDN Pulse Width
tPW
150
PDN“↑” to SDTO Delay (Note 20)
tPWV
typ
11.2896
16.9344
44.1
4128
Note 19. Except for I²S mode.
Note 20. This is the number of LRCK rising after PDN pin is pulled high.
max
12.8
19.2
50
55
tBLKL-50
80
80
Units
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
MS0171-E-00
-9-
2002/08