AK5356 Datasheet, PDF (19/22 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT ADC WITH MIC AMP & PGA

ASAHI KASEI
[AK5356]
Input Analog PGA Control
Addr Register Name
03H Input Analog PGA Control
Default
D7
ZEIP
0
D6
IPGA6
D5
IPGA5
D4
IPGA4
D3
IPGA3
28H
D2
IPGA2
D1
IPGA1
D0
IPGA0
ZEIP:
Select IPGA zero crossing operation
0: Disable (Default)
1: Enable
Writing to IPGA value at ZEIP = “1”, IPGA value of L/R channels changes by zero crossing detection
or timeout independently.
In the timeout cycle, it is possible to set in ZTM1-0 bit. When ZTM1-0 is “11”, timeout cycle is
2048/fs = 46.4ms (@fs=44.kHz). When ZEIP is “0”, IPGA changes immediately.
IPGA6-0: Input Analog PGA, 97 levels; 00H=MUTE
ON/OFF of zero crossing detection can be controlled by ZEIP bit.
DATA
60H
5FH
5EH
•
28H
27H
•
19H
18H
17H
16H
•
11H
10H
0FH
0EH
•
05H
04H
03H
02H
01H
00H
GAIN(dB)
Step
+28.0
+27.5
+27.0
•
+0.0
0.5dB
-0.5
•
-7.5
-8.0
-9.0
-10.0
•
1dB
-15.0
-16.0
-18.0
-20.0
•
2dB
-38.0
-40.0
-44.0
-48.0
4dB
-52.0
MUTE
Table 4. Input Gain Setting
Level
73
8
12
3
1
[ Writing to IPGA register at ZEIP = “1” continuously ]
When writing control register continuously, the change of IPGA should be written after zero crossing timeout. If
IPGA is changed by writing to control register before zero crossing detection, IPGA value of L/R channels may not
give a difference level.
MS0171-E-00
- 19 -
2002/08