AK5356 Datasheet, PDF (17/22 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT ADC WITH MIC AMP & PGA

ASAHI KASEI
[AK5356]
n Register Map
Addr
00H
01H
02H
03H
Register Name
Input Select
Power Management Control
Mode Control
IPGA Control
D7
0
0
MONO1
ZEIP
D6
PREG1
0
MONO0
IPGA6
D5
PREG0
0
ZTM1
IPGA5
D4
HPF
0
ZTM0
IPGA4
D3
RIN
0
0
IPGA3
D2
MICR
0
0
IPGA2
D1
LIN
PMADC
DIF
IPGA1
D0
MICL
PMMIC
0
IPGA0
All registers are reset at PDN = “L”, then inhibits writing to all registers.
For address from 04H to 1FH, data must not be written.
Unused bits must contain a “0” value.
n Register Definition
Input Select
Addr Register Name
00H Input Select
Default
D7
D6
D5
D4
0
PREG1 PREG0 HPF
0
1
0
0
D3
D2
D1
D0
RIN
MICR
LIN
MICL
0
1
0
1
PREG1-0: Select gain of Pre-Amp
00: +13dB
01: +18dB
10: +28dB (Default)
11: +33dB
Pre-Amp gain value of L/R channels change by zero crossing detection or timeout independently. Timeout
cycle is fixed to 2048/fs (=46.8ms @ fs = 44.1kHz). Zero crossing detection is done by IPGA block. When
PMADC bit is “0”, gain of Pre-Amp changes immediately.
HPF: Select ON/OFF of the digital HPF (0: ON, 1: OFF)
RIN:
MICR:
LIN:
MICL:
Select ON/OFF of Rch LINE input (0: OFF, 1: ON)
Select ON/OFF of Rch MIC input (0: OFF, 1: ON)
Select ON/OFF of Lch LINE input (0: OFF, 1: ON)
Select ON/OFF of Lch MIC input (0: OFF, 1: ON)
Power Management Control
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
01H Power Management Control
0
0
0
0
0
0
PMADC PMMIC
Default
0
0
0
0
0
0
1
1
PMADC: Power Management of IPGA and ADC
0: Power OFF
1: Power ON (Default)
PMMIC: Power Management of MIC Block (Pre-Amp, MIC Power and MVCM)
0: Power OFF
1: Power ON (Default)
When PDN pin goes “L”, all circuit in the AK5356 can be powered-down in no relation to PMADC and PMMIC bits.
When PMADC and PMMIC bits go “0”, all circuit in the AK5356 can be also powered-down. However, the contents
of control registers are held.
Except the case of PMADC=PMMIC= “0” or PDN pin = “L”, MCLK, BCLK and LRCK should not be stopped.
MS0171-E-00
- 17 -
2002/08