AK5356 Datasheet, PDF (12/22 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT ADC WITH MIC AMP & PGA

ASAHI KASEI
[AK5356]
OPERATION OVERVIEW
n System Clock
The clocks required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs, 40fs∼). The master clock (MCLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The Frequency of MCLK can be
input at 256fs or 384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically. *fs is sampling
frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these
clocks are not provided, the AK5356 may draw excess current and will not operate properly because it utilizes these clocks
for internal dynamic refresh of registers. If the external clocks are not present, the AK5356 should be placed in
power-down mode.
n Audio Data I/F Format
The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes,
MSB-first and 2’s compliment. The data format is set using the DIF bit. SDTO is latched by a falling edge of BCLK.
No. DIF bit
SDTO (ADC)
LRCK
BCLK
0
0
16bit MSB justified Lch: “H”, Rch: “L” = 32fs
20bit MSB justified Lch: “H”, Rch: “L” ≥ 40fs
16bit I²S compatible Lch: “L”, Rch: “H” = 32fs
1
1
20bit I²S compatible Lch: “L”, Rch: “H” ≥ 40fs
Table 1. Audio Data Format
Default
LRCK
012
BCLK(I:64fs)
12 13 14 19 20 21
31 0 1 2
12 13 14 19 20 21
31 0 1
SDTO(o)
19 18
01 2
BCLK(i:32fs)
876
0
19 18
876
0
19
3
9 10 11 12 13 14 15 0 1 2 3 3
9 10 11 12 13 14 15 0 1
SDTO (o)
19 18 17
11 10 9 8 7 6 5 4 19 18 17
11 10 9 8 7 6 5 4 19
19:MSB, 0:LSB
Lch Data
Figure 7. Audio Data Timing (No.0)
Rch Data
MS0171-E-00
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2002/08