AK2305 Datasheet, PDF (9/43 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for ISDN TERMINAL ADAPTER

ASAHI KASEI
[AK2305]
FUNCTIONAL DESCRIPTION
PCM INTERFACE
AK2305 supports the following types of format.
One of those is selected by PCMIF0 and PCMIF1 registers.
- Long Frame Sync(LF)
- Short Frame Sync(SF)
- GCI
- IDL
PCM data of both channels are multiplexed and interfaced through the common pins (DR0, DX0) in 2ch
Multiplex I/F mode. But in 2ch Independent I/F mode of LF or SF, it is also available to interface through the
independent pin(DR0/1,DX0/1) by channel.
Register of PCM interface mode selection
PCMIF1 PCMIF0
Interface
0
0
LF/SF (Non multiplex)
Frame sync
FS0,FS1
0
1
LF/SF (2ch multiplex) FS0,FS1
1
0
GCI (2ch multiplex)
FS0
1
1
IDL (2ch multiplex)
FS0
Input pin
DR0,DR1
DR0
DR0
DR0
Output pin
DX0, DX1
DX0
DX0
DX0
Remarks
Reset
FRAME SYNC SIGNAL(Frame Sync : FS)
Frame sync signal should be 8kHz clock. 8bits PCM data is accommodated in 1 frame (125us).
Though only FS0 is required (FS1 isn’t required) in the mode of GCI or IDL, both FS0 and FS1 are required in
the mode of LF or SF.
FIRST FS
It is used as the input clock of PLL. PLL generates all timing in this IC from this signal.
FS0 is assigned as First FS in the mode of GCI or IDL, and in the mode of LF or SF, it is assigned by the first FS
register.
1stFS
register
0
1
First FS
FS0
FS1
Remarks
Reset
Note
Keep supplying the first FS except for the state of all power down(PD=”H”). If the first FS is not supplied,
AK2305 loses timing; at a result, DTMFR and TONE GEN become not guaranteed to work normally.
BCLK
This clock decides the PCM data rate. See the following table of the relation between BCLK and PCM data rate.
PCM I/F mode
LF/SF/IDL
GCI
BCLK
F
2F
Rate of PCM
data
F
F
C0029-E-02
9
1999/8