AK2305 Datasheet, PDF (6/43 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for ISDN TERMINAL ADAPTER

ASAHI KASEI
Pin# Name
48 VFX0
47 GSX0
1 VRX0
2 VFX0
3 GSR0
10 GSR1
11 VFR1
12 VRX1
14 GSX1
13 VFX1
29 DX0
33 DR0
28 DX1
32 DR1
26 FS0
[AK2305]
PIN FUNCTION
I/O
Function
I Transmit analog input. Inverting input of transmit gain adjustment
amplifier for channel 0.
O Output of transmit gain adjustment amplifier for channel 0.
O Receive analog output of SMF for channel 0. This output can drive 10kΩ
and 50pF.
I Transmit analog input. Inverting input of transmit gain adjustment
amplifier for channel 0.
O Output of receive gain adjustment amplifier for channel 0.
O Output of receive gain adjustment amplifier for channel 1.
I Inverting input of receive gain adjustment amplifier for channel 1.
O Receive analog output of SMF for channel 1. This output can drive 10kΩ
and 50pF.
O Output of transmit gain adjustment amplifier for channel 1.
I Transmit analog input. Inverting input of transmit gain adjustment
amplifier for channel 1.
O Serial output of PCM data of ch0.
In Long Frame / Short Frame mode, output PCM data of ch0.
In GCI / IDL mode, output PCM data of ch0 is multiplexed with ch1. The
PCM data rate is synchronized with BCLK.
See “PCM INTERFACE” from page 9.
This output remains in the high impedance state except for the period of
transmitting PCM data.
I Serial input of PCM data of ch0.
In Long Frame / Short Frame mode, input PCM data of ch0.
In GCI / IDL mode, input PCM data of ch0 is multiplexed with ch1. The
PCM data rate is synchronized with BCLK.
See “PCM INTERFACE” from page 9.
O Serial output of PCM data of ch1.
In Long Frame / Short Frame mode, output PCM data of ch1.
The PCM data rate is synchronized with BCLK.
See “PCM INTERFACE” from page 9.
This output remains in the high impedance state except for the period of
transmitting PCM data.
In 2ch multiplexd mode, this pin remains in the high impedance state.
O Serial input of PCM data of ch1.
In Long Frame / Short Frame mode, input PCM data of ch1. The PCM
data rate is synchronized with BCLK.
See “PCM INTERFACE” from page 9.
In GCI / IDL mode, this pin is pulled down to VSS.
I Frame sync input for channel 0.
FS0 must be 8KHz clock synchronized in BCLK.
C0029-E-02
6
1999/8