AK2305 Datasheet, PDF (8/43 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for ISDN TERMINAL ADAPTER

ASAHI KASEI
[AK2305]
CIRCUIT DESCRIPTION
Block
AMPT0,1
AMPR0,1
AAF
A/D
D/A
SMF
BGREF
TONE GEN 0
TONE GEN 1
SWITCH
Sn(n=1-9)
DTMF
Receiver0,1
VR0T/R
VR1T/R
VRTN
SERIAL I/F
PLL
PCM I/F
Function
Op-amp for input gain adjustment. This op-amp is used as an inverting amplifier.
Adjusting the gain with external resistors. The resistor larger than 10kΩ is
recommended for the feedback resistor.
<NOTE>
AMP0(1) becomes automatically power down, when both CODEC ch0(1) and
DTMFR0(1) are power down.
Op-amp for output gain adjustment. This op-amp is used as an inverting amplifier.
Adjusting the gain with external resistors. The resistor larger than 10kΩ is
recommended for the feedback resistor.
Integrated anti-aliasing filter which prevents signals around the sampling rate
from folding back into the voice band. AAF is a 2nd order RC low-pass filter.
Converts analog signal to 8bit PCM data according to the companding schemes of
ITU recommendation G.711; A-law or u-law. The band limiting filter is also
integrated. The selection of companding schemes is set by ALAWN register as
follows:
"H": u-Law
"L": A-Law
Expands 8bit PCM data according to A-law or u-law. The selection of companding
schemes is set by ALAWN register as follows:
"H": u-Law
"L": A-Law
Extracts the inband signal from D/A output. It also corrects the sinx/x effect of
D/A output.
Provides the stable analog ground voltage (2.4V) using an on-chip band-gap
reference circuit which is temperature compensated.
Generates two kinds of tone; 400Hz and 1300Hz. Tone selection is defined by
registers. ON/OFF of tone output is controlled by TNOE0/1.
Controls output signals from VRX0, VRX1, TNOUT pins. Each switch is controlled
by register.
Detects and decodes the DTMF tone. ON/OFF of decoded output is controlled by
DTOE.
Gain selects of analog I/O signals. It is posibble to select gain from 0dB to -12dB
(3dB/step* 5steps). Gain is defined by register.
Interface to internal register by using SCLK, DATA, and CS pins.
1word=14bit; Instruction code: 2bit, address: 3bit, data: 9bit(1dummy bit
included).
PLL generates system clock of AK2305. Reference clock is FSn (8KHz). More than
0.22uF of an external capacitance should be connected between LPC and AVSS.
PCM data rate is available for 64xN(N = 1 to 64)kHz which synchronizes with
BCLK. Data format is selected in four types(Long Frame, Short Frame, GCI, IDL).
2ch PCM data are interfaced through DR0,1 and DX0,1 in non multiplexed mode
or DR0 and Dx0 in multiplexed mode.
C0029-E-02
8
1999/8