AK2305 Datasheet, PDF (11/43 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for ISDN TERMINAL ADAPTER

ASAHI KASEI
[AK2305]
INTERFACE TIMING
<Non Multiplex>
PCM data of each channel are interfaced by each I/O pins(DX0 and DR0/DX1 and DR1) at the format of 8bits
in the period of 1 frame(125us) which synchronizes with the FSn(n=0,1). The timing of FS0 and FS1 can be set
at optionally as far as they synchronize with BCLK.
NOTE) First FS and Second FS
Only when BCLK=64kHz, it is possible to input the same clock to the first FS and the second FS. Except for
64kHz BCLK, 8 clock of BCLK x n (n=1-63 integral numbers) intervals of n slots are needed.
BCLK=4096kHz ( First FS = FS0 )
FS0
FS1
SLOT
DX0
DR0
DX1
DR1
1234
ch0
output
ch0
input
ch1
output
ch1
input
63 64 1 2 3 4
ch0
output
ch0
input
ch1
output
ch1
input
BCLK=64kHz(LF) ( FS0 and FS1 at the same timing, First FS = FS0 )
FS0,FS1
BCLK
DX0
DR0
DX1
DR1
1234
1234
1234
1234
56781234
56781234
56781234
56781234
BCLK=64kHz(LF) ( First FS = FS0 )
FS0
FS1
BCLK
DX0
DR0
1234
1234
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
DX1
DR1
C0029-E-02
123
4
56
781234
123
4
56
781234
11
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