AK2305 Datasheet, PDF (22/43 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for ISDN TERMINAL ADAPTER

ASAHI KASEI
[AK2305]
SERIAL INTERFACE
The internal registers can be read/written with SCLK, DATA, and CS pins.
1word consists of 14bits. The first 2bits are the instruction code which specifies read/write.
The following 3bits specify the address. The rest of 8bits are for setting registers.
B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
I1 I0 A2 A1 A0 * D7 D6 D5 D4 D3 D2 D1 D0
Instruc-
tion code
(2bit)
Address
(3bit)
*
Data for setting internal registers
(8bit)
*)Dummy bit for adjusting the I/O timing when reading data.
INSTRUCTION CODE
I1
I0
1
0
1
1
Other codes
Read/Write
Read
Write
No action
SCLK and WRITE / READ
(1) Input data are loaded into the internal shift register at the rising edge of SCLK.
(2) The rising edge of SCLK is counted after the falling edge of CS .
(3) When CS is “L” and more than 14 SCLK pulses:
[WRITE] Data are loaded into the internal register at the rising edge of the SCLK 14^th pulse.
[READ] DATA pin is switched to an input pin at the falling edge of the SCLK 14^th pulse.
CS and WRITE / READ CANCELLATION
(1) WRITE is cancelled when CS goes up before the rising edge of the SCLK 14^th pulse.
(2) READ is cancelled when CS goes up before the falling edge of the SCLK 14^th pulse.
SERIAL WRITE / READ (SERIAL ACCESS)
(1) CS must go up to “H” before the next access in successive access.
(2) When the next access is going to be done , if CS remains to be “L”, successive access can not be done.
C0029-E-02
22
1999/8