AK2305 Datasheet, PDF (34/43 Pages) Asahi Kasei Microsystems – Dual PCM CODEC for ISDN TERMINAL ADAPTER

ASAHI KASEI
[AK2305]
Timing Specification
Unless otherwise noted, the specification applies for TA = -40 to +85^oC, DVDD = AVDD = 5V±5%,DVSS = AVSS
= 0V and FS0,FS1 = 8kHz. All timing parameters are measured at VOH = 2.0V and VOL =0.7V.
Lomg Frame,Short Frame,GCI, IDL Timing
Parameter
Symbol Min Typ Max Unit Ref fig
FS Frequency
1/t_PF
-
8
- kHz
BCLK Frequency
1/t_PB 64
4096 kHz
BCLK Pulse Width High
t_{W BH}
80
ns
BCLK Pulse Width Low
Rising Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1)
Falling Time: (BCLK,FS0,FS1,DX0,DX1,DR0,DR1)
Hold Time: BCLK Low to FS High
t_{W BL}
80
t_R
t_F
t_HBF
40
ns
40 ns _Fig.2
Fig.3
40 ns _Fig.4
ns ^Fig.5
Setup Time: FS High to BCLK Low
t_SFB
70
ns
Setup Time: DR to BCLK Low
Hold Time: BCLK Low to DR
Delay Time: BCLK High to DX valid
t_SDB
40
t_HBD
40
(Note1) t_DBD
ns
ns
60 ns
Long Frame
Hold Time: 2^nd period of BCLK Low to FS Low
t_HBFL
40
Delay Time: FS or BCLK High, whichever is later,to DX valid
(Note1)
t_DZFL
Delay Time: FS or BCLK Low, whichever is later, to DX High-
Z (Note1)
t_DZCL
10
FS Pulse Width Low
t_WFSL
1
ns
60 ns
Fig.2
60 ns
BCLK
Short Frame
Hold Time: BCLK Low to FS Low
Setup Time: FS Low to BCLK Low
Delay Time: BCLK Low to DX High-Z
t_HBFS
40
t_SFBS
40
(Note1) t_DZCS 10
ns
ns Fig.3
60 ns
GCI
BCLK Frequency
1/t_PB 512
4096 kHz
Delax Time: Second BCLK Low to DX High-Z
Setup Time: DR to Second BCLK High
Hold Time: Second BCLK High to DR
t_DZCG
10
t_SDBG
40
t_HBDG
40
60 ns
Fig.4
ns
ns
IDL
BCLK Frequency
1/t_PB 256
4096 kHz Fig.5
Note1) When with 150pF cap, and two LSTTL operating.
C0029-E-02
34
1999/8