AK8856VN Datasheet, PDF (86/98 Pages) Asahi Kasei Microsystems – NTSC/PAL Video Decoder

ASAHI KASEI
[AK8856 Preliminary Data Sheet]
PGA Control Register (R/W) [Sub Address 0x05]
Sets PGA gain; when the AGC function is enabled, the gain value for the AGC is set by this register.
Sub Address 0x05
bit 7
bit 6
Reserved
PGA6
0
0
bit 5
PGA5
0
bit 4
bit 3
PGA4
PGA3
Default Value
1
0
bit 2
PGA2
1
Default Value: 0x15
bit 1
bit 0
PGA1
PGA0
0
1
PGA Control Register Definition
BIT Register Name
bit 0
PGA0
~
~
PGA Gain Set
bit 6
PGA6
bit 7
Reserved
Reserved
R/W
Definition
Sets gain of PGA:
R/W _{PGA can be adjusted in approximately 0.1 dB / step.}
R/W Reserved
Note) When reading this register while the AGC is enabled, the PGA value which is set by AGC is returned. It is possible for
the user to write a value (user-set-value) while the AGC is enabled, but its value is not written to the PGA. A returned value
from the register read operation is the same AGC set value. When the AGC is disabled, the user-set-value is valid, and its
value is returned by a Register Read operation.
MS0522-E-00
86
2006/Dec