AK8856VN Datasheet, PDF (84/98 Pages) Asahi Kasei Microsystems – NTSC/PAL Video Decoder

ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Control 1 Register (R/W) [Sub Address 0x03]
Control Register
Sub Address 0x03
bit 7
bit 6
Reserved
VDFLD
0
0
bit 5
AGCTR
0
bit 4
bit 3
AGCC1
AGCC0
Default Value
0
0
bit 2
CKILSEL1
Default Value: 0x00
bit 1
bit 0
CKILSEL0
YCSEP
0
0
0
Control 1 Register Definition
BIT Register Name
bit 0
YCSEP
YC Separation Set bit
bit 1
CKILSEL0
~
~
Color killer Select bit
bit 2
CKILSEL1
bit 3
AGCC0
~
~
AGC Coring Level
bit 4
AGCC1
bit 5
AGCTR
AGC Transient Level
bit 6
VDFLD
VD Field Select bit
bit 7
Reserved
Reserved bit
R/W
Definition
Selects YC separation method:
Operation of YC separation is fixed by a selected
input signal type and output data size.
R/W _{For NTSC & QVGA,CIF,QCIF, QVGAL,CIFL:}
0 : primary YC separation (AK8855 compatible)
1 : Y by primary YC separation filter and C by
two dimensional YC separation filter
Sets “ ON “ condition of Color-Killer:
00 : when at [01] condition or at [10] condition
01 : locked Color Decode PLL becomes
R/W
out-of-lock condition.
10 : Color Burst signal level becomes lower than
approximately –23 dB.
11 : Reserved
Sets AGC Coring level
00 : +/_ 2 LSB Coring level
R/W 01 : +/_ 3 LSB Coring level
10 : +/_ 4 LSB Coring level
11 : no Coring level
Sets transient conditions of Sync AGC and Peak
AGC:
R/W _{0 : Quick}
1 : Slow
Sets the type of output signal on VD / VAF / FIELD
pin:
VAF signal is always output on this pin in Camera
R/W _{interface mode.}
0 : VD / VAF signal is output
1 : FIELD signal is output
R/W
MS0522-E-00
84
2006/Dec