AK8856VN Datasheet, PDF (76/98 Pages) Asahi Kasei Microsystems – NTSC/PAL Video Decoder

ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Digital Pixel Interpolator
The Digital Pixel Interpolator is used to align vertical pixels (the interpolation block used is not compatible with the
AK8855/AK8880. The AK8856 Interpolator is the same one used for theAK8851).
YC Delay
YC delay time is adjustable. In tuner output mode, there is a condition where the C signal is delayed from the Y
signal. The adjustable YC Delay function is effective for this condition. The delay amount is adjustable with a
single, internal processing clock unit. The setting is in 2’s complement format.
The delay amount is adjusted by setting the YC Delay Control Register (R/W) [Sub Address 0x0B].
Sub Address 0x0B
bit 7
bit 6
Reserved
Reserved
0
0
bit 5
Reserved
0
bit 4
bit 3
Reserved
Reserved
Default Value
0
0
bit 2
YCDELAY2
Default Value : 0x00
bit 1
bit 0
YCDELAY1 YCDELAY0
0
0
0
YCDELAY2 :YCDELAY0
101
110
111
000
001
010
011
Delay amount
Y is delayed from C by 3 clock cycles
Y is delayed from C by 2 clock cycles
Y is delayed from C by 1 clock cycles
No delay between Y and C
Y is advanced from C by 1 clock cycles
Y is advanced from C by 2 clock cycles
Y is advanced from C by 3 clock cycles
Note
Delay amount depends on the selected
output mode.
VGA/QVGA/QVGA Rotated/CIF
Rotated : 12. 2727 MHz
601/CIF/QCIF : 13.5 MHz
Delay amount is based on the selected clock
mode.
MS0522-E-00
76
2006/Dec