AK8856VN Datasheet, PDF (72/98 Pages) Asahi Kasei Microsystems – NTSC/PAL Video Decoder

ASAHI KASEI
[AK8856 Preliminary Data Sheet]
(3) 656 Interface
The AK8856 is designed for applications where the video data is typically processed with an MPEG algorithm.
As such, it is capable of supporting a specific subset of the BT656 data interface. In 656 mode, the AK8856
generates synchronization codes SAV and EAV to indicate active video data. These codes are interpreted by the
external digital video processor. In this mode, HD, DV, and DVALID signals are held low. The HD and DV
signals can be read through a register setting.
The relationship between the interface and the output format register is described here. Related registers are
[OFORM1 : OFORM0] bits and [OIF2 : OIF0] bits of the Output Control 1 Register (R/W) [Sub Address 0x01].
Interface modes are set, regardless of OFORM register setting.
OIF[0] = 1'b0 : without SAV/EAV
1'b1 : with SAV/EAV (at OFORM [ 2:0 ] = = 3’b 110 “, ITU-R BT.656)
OIF[1] = 1'b0 : Camera I/F
1'b1 : HD/VD/DVALID I/F
The Rec.656 mode supported by the AK8855 can be ITU-R BT. 656 compatible by setting OIF with SAV / EAV
code (OIF [0] = = 1’b 1) when OFORM [2:0] = = 3’ b 110. In all other codes, the V-bit of SAV / EAV becomes
“0“ during Vertical Active Video region only.
When OIF [1:0] = = 2’b 11, the interface mode is HD / VD / DVALID interface with SAV / EAV code in the
AK8856. In addition, when OFORM [2:0] = = 3’b 110, SAV / EAV is output in ITU-R BT.656 compatible fashion.
By setting the [TRSVSEL] bit of the Output Control 1 Register (R/W) [Sub Address 0x01], it is possible to
change the V-bit shift point of the 656 specified Video Timing Reference code (SAV / EAV) separately from the
values referred to in the previous section. By properly setting the [TRSVSEL] bit, it is possible to make the shift
point of V-bit compatible with ITU-R BT.656-3 or ITU-R BT.656-4 and SMPTE125M.
Bit allocation of Output Control 1 Register
Sub Address 0x01
bit 7
bit 6
VDPSUP TRSVSEL
0
0
bit 5
OIF1
0
bit 4
bit 3
OIF0
LIMIT601
Default Value
0
0
bit 2
OFORM2
0
Default Value : 0x00
bit 1
bit 0
OFORM1
OFORM0
0
0
[TRSVSEL] bit
This is a control bit to specify V-bit handling in the Rec 656 EAV / SAV code.
<V-bit value in Rec. 656 TRS signal and Line relation>
NTSC(525Lines)
PAL(625Lines)
V-bit
TRSVSEL = 0
Based on ITU-R
Bt.656-3
TRSVSEL = 1
Based on ITU-R
Bt.656-4 and
SMPTE125M
TRSVSEL = 0
TRSVSEL = 1
V-bit = 0
Line10 ~ Line263
Line273 ~ Line525
Line20 ~ Line263
Line283 ~ Line525
Line23 ~ Line310
Line336 ~ Line623
V-bit = 1
Line1 ~ Line9
Line264 ~ Line272
Line1 ~ Line19
Line264 ~ Line282
Line1 ~ Line22
Line311 ~ Line335
Line624 ~ Line625
MS0522-E-00
72
2006/Dec