AK8856VN Datasheet, PDF (85/98 Pages) Asahi Kasei Microsystems – NTSC/PAL Video Decoder

ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Control 2 Register (R/W) [Sub Address 0x04]
Control Register
Sub Address 0x04
bit 7
bit 6
CNTSEL
NSIGDEF
0
0
bit 5
ODEV
0
bit 4
bit 3
FRMRT1
FRMRT0
Default Value
0
0
bit 2
COLKIL
0
Default Value: 0x00
bit 1
bit 0
ACC
AGC
0
0
Control 1 Register Definition
BIT Register Name
bit 0
AGC
AGC set bit
bit 1
ACC
ACC set bit
bit 2
COLKIL
Color Killer Set bit
bit 3
FRMRT0
~
~
Frame Rate Set bit
bit 4
FRMRT1
bit 5
ODEV
ODD Even Select bit
bit 6
NSIGDEF
NSIG Define Mode
bit 7
CNTSEL
Contrast mode select bit
R/W
Definition
R/W ^{0 : AGC Disable (PGA manual setting is enabled )}
1 : AGC Enable
R/W ^{0 : ACC Disable}
1 : ACC Enable
R/W ^{0 : Color Killer enabled}
1 : Color Killer disabled
Sets Frame Rate [Frames / sec]
FRMRT 1:0 (525 / 625)
00: 30/25
R/W _{01: 15/12.5}
10: 7.5/6.25
11: Reserved
Sets decode field for QVGA / CIF / QCIF decoding:
R/W 0 : Decode Odd Field
1 : Decode Even Field
Sets NSIG pin output condition.
0 : when both Horizontal and Vertical
R/W
synchronizations lose sync, NSIG goes high (output
shifts to self-running mode)
1 : when Vertical synchronization loses sync, NSIG
goes high
Sets the start point for contrast adjustment
0 : Contrast varies, starting at Luminance level of 128
R/W (gray) as a center value
1 : Contrast varies, starting at Luminance level of 16
(black) as a center value
MS0522-E-00
85
2006/Dec