AK8856VN Datasheet, PDF (83/98 Pages) Asahi Kasei Microsystems – NTSC/PAL Video Decoder

ASAHI KASEI
[AK8856 Preliminary Data Sheet]
Output Control 2 Register (R/W) [Sub Address 0x02]
Sets polarity of output pin and to set output condition when no input signal is fed.
Functional modification has been made on bit 7 of this register from the AK8855.
Sub Address 0x02
Default Value: 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NSIGMD1 NSIGMD0 DVALACT
HVACT
CLKINV
DVALIDP
VDP
HDP
Default Value
0
0
0
0
0
0
0
0
Output Control 2 Register Definition
BIT Register Name
bit 0
HDP
HD pin Polarity set bit
bit 1
VDP
VD pin Polarity set bit
bit 2
DVALDP
DVALID pin Polarity set bit
bit 3
CLKINV
CLK invert set bit
bit 4
HVACT
HD/VD action bit
bit 5
DVALACT
DVALID action bit
bit 6
NSIGMD0
~
~
No SiGnal Output MoDe
bit 7
NSIGMD1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Definition
Sets polarity of HD signal:
0: Active Low
1: Active High
Sets polarity of VD signal:
0: Active Low
1: Active High
Sets polarity of DVALID signal:
0: Active Low
1: Active High
Sets polarity of CLKO:
0: normal output (data should be taken at the rising
edge)
1: phase relation between data and clock is inverted
(data should be taken at the falling edge).
Outputs HD & VD in EAV / SAV Interface mode:
no output ( fixed to low )
1 : to output
Outputs DVALID signal in EAV / SAV Interface
mode:
0: no output ( fixed to low )
1: to output
Sets output condition when no signal input
condition is detected:
00 : Output Black level
01 : Output Blue level (Blue back)
10 : Output input condition directly as is(“ Sand-
Storm “ condition).
11 : Reserved
MS0522-E-00
83
2006/Dec