AKD4122 Datasheet, PDF (8/36 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4122

ASAHI KASEI
[AKD4122]
3. All clocks are fed through the 10pin port
When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2)
should be short.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
(2-2) Master mode
MCLK must be provided in the master mode.
1. When using DIR function of AK4114 (U13)
When using PORT6 (DIR2), nothing should be connected to J2 (EXT2) and PORT7 (DSP2). Set JP18
(MCLK2) to the “DIR” in order to supply MCLK to the AK4122.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
• SW3 setting (See Table 7, 8, 9)
Upper-side is “H” and lower-side is “L”.
SW3 No.
1
2
3
4
Name
OCKS
DIF0
DIF1
DIF2
ON (“H”)
OFF (“L”)
AK4114 Master Clock Output Setting
Refer to Table 8
AK4114 Audio Format Setting
Refer to Table 9
Table 7. SW3 setting
Mode
0
1
OCKS MCKO1 X’tal
0
256fs
256fs
1
512fs
512fs
Table 8. AK4114 MCKO1 setting
fs
∼ 96kHz
∼ 48kHz
Mode
0
1
Audio I/F Format
AK4114
DIF2 DIF1 DIF0
AK4122
IDIF1 IDIF0
24bit, MSB justified
1
1
0
0
1
24bit, I²S Compatible
1
1
1
1
0
Table 9. AK4114 Audio interface format setting
* IDIF1-0 of the AK4122 is set by the register.
<KM071100>
-8-
2003/06