AKD4122 Datasheet, PDF (17/36 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4122

ASAHI KASEI
[AKD4122]
(5-2) Master mode
MCLK must be provided in the master mode.
1. When using DIT function of AK4114 (U14)
When using X’tal (X2) and PORT10 (DIT3), nothing should be connected to PORT9 (DSP3). Set JP21
(OMCLK) to the “DIT” in order to supply MCLK to the AK4122. When MCLK frequency is changed, the
value of X’tal (X2) frequency should be changed according to MCLK frequency.
JP19
BICK
JP20
LRCK
JP21
OMCLK
JP25
TST
DIT EXT DIT EXT DIT EXT OMCK TST
• SW4 setting (See Table 23, 24, 25)
Upper-side is “H” and lower-side is “L”.
SW4 No.
1
2
Name
OCKS
DIF0
ON (“H”)
OFF (“L”)
AK4114 Master Clock Output Setting
Refer to Table 24
AK4114 Audio Format Setting
Refer to Table 25
Table 23. SW4 setting
Mode
0
1
OCKS MCKO1 X’tal
fs
0
256fs
256fs
∼ 96kHz
1
512fs
512fs
∼ 48kHz
Table 24. AK4114 MCKO1 setting
Mode
Audio I/F Format
AK4114 AK4122
DIF0
ODIF
0
24bit, MSB justified
0
0
1
24bit, I²S Compatible
1
1
Table 25. AK4114 Audio interface format setting
* ODIF of the AK4122 is set by the register.
<KM071100>
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2003/06