AKD4122 Datasheet, PDF (12/36 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4122

ASAHI KASEI
[AKD4122]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ
When using PORT7 (DSP2), nothing should be connected to PORT6 (DIR2). MCLK is input from J2 (EXT2),
BICK and LRCK are supplied by using the clock dividing circuit on this evaluation board to the AK4122. Set
JP18 (MCLK2) to the “EXT” when MCLK is supplied to the AK4122.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
• Clock Setting
MCLK is input from J2 (EXT2), BICK and LRCK are generated by using the clock dividing circuit. JP4
(DIV2) and JP5 (CLK2) are set by referring to Table 14. JP6 (BCFS) selects the frequency of BICK. JP7
(EXT2) should be open.
JP4
DIV2
JP5
CLK2
JP6
BCFS
JP7
EXT2
256 384 64fs 32fs
fs
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
MCLK
JP4(DIV2)
256fs = 8.192MHz
256
384fs = 12.288MHz
Open
512fs = 16.384MHz
512
768fs = 24.576MHz
768
256fs = 11.2896MHz
256
384fs = 16.9344MHz Open
512fs = 22.5792MHz
512
768fs = 33.8688MHz
768
256fs = 12.288MHz
256
384fs = 18.432MHz
Open
512fs = 24.576MHz
512
768fs = 36.864MHz
768
256fs = 22.5792MHz
256
384fs = 33.8688MHz Open
256fs = 24.576MHz
256
384fs = 36.864MHz
Open
Table 14. Example for Clock setting
JP5(CLK2)
256
384
256
256
256
384
256
256
256
384
256
256
256
384
256
384
3. All clocks are fed through the 10pin port
When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2)
should be short.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
<KM071100>
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2003/06