AKD4122 Datasheet, PDF (16/36 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4122

ASAHI KASEI
[AKD4122]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ
When using PORT9 (DSP3), nothing should be connected to PORT10 (DIT3). MCLK is input from J3
(EXT3), BICK and LRCK are supplied by using the clock dividing circuit on this evaluation board to the
AK4122. Set JP21 (OMCLK) to the “EXT” when MCLK is supplied to the AK4122.
JP19
BICK
JP20
LRCK
JP21
OMCLK
JP25
TST
DIT EXT DIT EXT DIT EXT OMCK TST
• Clock Setting
MCLK is input from J3 (EXT3), BICK and LRCK are generated by using the clock dividing circuit. JP8
(DIV3) and JP9 (CLK3) are set by referring to Table 22. JP10 (EXT3) should be open.
JP8
DIV3
JP9
CLK3
JP10
EXT3
256 384
fs
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
MCLK
JP8(DIV3)
256fs = 8.192MHz
256
384fs = 12.288MHz
Open
512fs = 16.384MHz
512
768fs = 24.576MHz
768
256fs = 11.2896MHz
256
384fs = 16.9344MHz Open
512fs = 22.5792MHz
512
768fs = 33.8688MHz
768
256fs = 12.288MHz
256
384fs = 18.432MHz
Open
512fs = 24.576MHz
512
768fs = 36.864MHz
768
256fs = 22.5792MHz
256
384fs = 33.8688MHz Open
256fs = 24.576MHz
256
384fs = 36.864MHz
Open
Table 22. Example for Clock setting
JP9(CLK3)
256
384
256
256
256
384
256
256
256
384
256
256
256
384
256
384
3. All clocks are fed through the 10pin port
When using PORT9 (DSP3), nothing should be connected to PORT10 (DIT3). Set JP25 (TST) to the “OMCK”
when MCLK is supplied to the AK4122. JP10 (EXT3) should be short.
JP19
BICK
JP20
LRCK
JP21
OMCLK
JP25
TST
DIT EXT DIT EXT DIT EXT OMCK TST
<KM071100>
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2003/06