AKD4122 Datasheet, PDF (11/36 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4122

ASAHI KASEI
[AKD4122]
(4) Setting for Output port (AK4122 PORT2)
(4-1) Slave mode
1. When using DIT function of AK4114 (U13)
When using X’tal (X1) and PORT8 (DIT2), nothing should be connected to PORT6 (DIR2) and PORT7
(DSP2). Set JP18 (MCLK2) to the “DIR” when MCLK is supplied to the AK4122. When MCLK frequency is
changed, the value of X’tal (X1) frequency should be changed according to MCLK frequency.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
• SW3 setting (See Table 11, 12, 13)
Upper-side is “H” and lower-side is “L”.
SW3 No.
1
2
3
4
Name
ON (“H”)
OFF (“L”)
OCKS
AK4114 Master Clock Output Setting
Refer to Table 12
DIF0
DIF1
DIF2
AK4114 Audio Format Setting
Refer to Table 13
Table 11. SW3 setting
Mode
0
1
OCKS MCKO1 X’tal
fs
0
256fs
256fs
∼ 96kHz
1
512fs
512fs
∼ 48kHz
Table 12. AK4114 MCKO1 setting
Default
Mode
0
1
2
3
Audio I/F Format
AK4114
DIF2 DIF1 DIF0
AK4122
IDIF1 IDIF0
24bit, MSB justified
1
0
0
0
0
24bit, MSB justified
1
0
0
0
1
24bit, I²S Compatible
1
0
1
1
0
24bit, MSB justified
1
0
0
1
1
Table 13. AK4114 Audio interface format setting
Default
* IDIF1-0 of the AK4122 is set by the register.
<KM071100>
- 11 -
2003/06