AKD4122 Datasheet, PDF (10/36 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4122

ASAHI KASEI
(3) Setting for Input port (AK4122 DIR)
(3-1) Setting for DIR input
The signal source of AK4122’s DIR can be set by JP2 (RX) and JP3 (RX1-4).
PORT3
3
VCC
GND
OUT
2
1
DIR
J1
RX
VCC
L1
47u
C6
0.1u
R24
470
R25 C11
75 0.1u
OPT
JP2
RX
BNC
JP3
RX1
RX2
RX3
RX4
RX1-4
RX1
RX2
RX3
RX4
Figure 8. DIR input circuit
JP2
JP2
RX
RX
RX BNC RX BNC
Optical
Coaxial
Figure 9. JP2 setting
JP3
RX1-4
RX1
RX2
RX3
RX4
RX1
JP3
RX1-4
JP3
RX1-4
RX1
RX1
RX2
RX2
RX3
RX3
RX4
RX4
RX2
RX3
Figure 10. JP3 setting
JP3
RX1-4
RX1
RX2
RX3
RX4
RX4
(3-2) Setting for DIR through signal
DIR through signal of the AK4122 is output to TX pin via PORT2 (TX).
VCC
PORT2
TX
3
2
IN
VCC
C1
0.1u
1 _GND
TX
Figure 11. DIR through signal
[AKD4122]
<KM071100>
- 10 -
2003/06