AK4555 Datasheet, PDF (7/17 Pages) Asahi Kasei Microsystems – Low Power & Small Package 20bit ΔΣ CODEC

ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=1.6 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
256fs/384fs/512fs/768fs
fCLK
2.048
1024fs
fCLK
2.048
Duty Cycle
dCLK
40
LRCK Timing
Frequency
fs
8
Duty Cycle
Duty
45
Serial Interface Timing
SCLK Period
(8kHz ≤ fs ≤ 33kHz)
tSCK
1/(96fs)
(33kHz < fs ≤ 50kHz)
tSCK
312.5
SCLK Pulse Width Low
tSCKL
130
Pulse Width High
tSCKH
130
LRCK Edge to SCLK “↑”
(Note 8)
tLRS
50
SCLK “↑” to LRCK Edge
(Note 8)
tSLR
50
SCLK “↓” to SDTO
tDSS
-
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Reset Timing
PWADN or PWDAN Pulse Width
tPW
150
PWADN “↑” to SDTO Valid (Note 9)
tPWV
-
typ
-
-
-
44.1
-
-
-
-
-
-
-
-
-
-
-
2081
Note 8. SCLK rising edge must not occur at the same time as LRCK edge.
Note 9. These cycles are the number of LRCK rising from PWADN rising.
[AK4555]
max
Units
38.4
MHz
25.6
MHz
60
%
50
kHz
55
%
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
80
ns
-
ns
-
ns
-
ns
-
1/fs
MS0363-E-01
-7-
2005/08