AK4555 Datasheet, PDF (12/17 Pages) Asahi Kasei Microsystems – Low Power & Small Package 20bit ΔΣ CODEC

ASAHI KASEI
[AK4555]
SYSTEM DESIGN
Figure 6 shows the system connection diagram. An evaluation board[AKD4555] is available which demonstrates
application circuit, optimum layout, power supply arrangements and measurement results.
0.1u
Rch In
+
Lch In
+
Analog Supply
1.6 ∼ 3.6V
10u ₊
1 VCOM
AOUTR 16
2 AINR
AOUTL 15
3
4
0.1u
5
AINL
VSS
VDD
AK4555 ^{PWDAN 14}
PWADN 13
Top View _{SCLK 12}
6 DEM0
MCLK 11
7 DEM1
LRCK 10
8 SDTO
SDTI 9
Mode
Control
Analog Ground
Reset
Reset
Controller
System Ground
Figure 6. System Connection Diagram Example
Notes:
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
MS0363-E-01
- 12 -
2005/08