AK4555 Datasheet, PDF (14/17 Pages) Asahi Kasei Microsystems – Low Power & Small Package 20bit ΔΣ CODEC

ASAHI KASEI
[AK4555]
„ Layout Pattern Example
AK4555 requires careful attention to power supply and grounding arrangements to optimize performance.
(Please refer to AKD4555 Evaluation Board layout pattern.)
1. VDD pin should be supplied from analog power supply on system, and VSS pin should be connected to analog
ground on system. The AK4555 is placed on the analog ground plane, and near the analog ground and digital ground
split. And analog and digital ground planes should be only connected at one point. The connection point should be
near to the AK4555.
2. VDD pin should be distributed from the point with low impedance of regulator etc.
3. The series resistors are prevent on the clock lines to reduce overshoot and undershoot. To avoid digital noise
coupling to analog circuit in the AK4555, a 10pF ceramic capacitor on MCLK pin is connected with digital ground.
4. 0.1µF ceramic capacitors of VDD-VSS pins and VCOM-VSS pins should be located as close to the AK4555 as
possible. And these lines should be the shortest connection to pins.
0.1u
Rch In
+
1 VCOM
AOUTR 16
Lch In
+
Analog Supply
1.6 ∼ 3.6V
2 AINR
AOUTL 15
3 AINL _AK4555 PWDAN 14
4 VSS
PWADN 13
+
5 VDD ^{Top View} SCLK 12
10u 0.1u
6 DEM0
MCLK 11
7 DEM1
LRCK 10
Analog Ground
8 SDTO
SDTI 9
Digital Ground
51
Mode Control
Reset &Power-down
51
51
10P
51
Controller
51
Figure 7. Layout Pattern Example
MS0363-E-01
- 14 -
2005/08