AK4555 Datasheet, PDF (13/17 Pages) Asahi Kasei Microsystems – Low Power & Small Package 20bit ΔΣ CODEC

ASAHI KASEI
[AK4555]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling
capacitors should be as near to the AK4555 as possible, with the small value ceramic capacitor being nearest.
2. Voltage Reference
The input to VDD voltage sets the analog input/output range. A 0.1µF ceramic capacitor is connected to VDD and VSS
pins, normally. VCOM is a signal ground of this chip. A 0.1µF ceramic capacitor attached to VCOM pin eliminates the
effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clock, should be
kept away from the VDD and VCOM pins in order to avoid unwanted coupling into the AK4555.
3. Analog Inputs
ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and
nominally 0.6xVDD Vpp(typ). The ADC output data format is 2’s compliment.
The AK4555 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. The AK4555 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The output signal range scales with the
supply voltage and nominally 0.6xVDD Vpp(typ). The DAC input data format is 2’s compliment. The output voltage is a
positive full scale for 7FFFFH(@20bit) and a negative full scale for 80000H(@20bit). The ideal output is VCOM voltage
for 00000H(@20bit). If the noise generated by the delta-sigma modulator beyond the audio band would be the problem,
the attenuation by external filter is required.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
MS0363-E-01
- 13 -
2005/08