AK4634EN Datasheet, PDF (60/94 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK -AMP

[AK4634]
(2)-2. READ Operations
Set the R/W bit = “1” for READ operation of the AK4634. After a transmission of data, if the master generates an
acknowledge instead of terminating a write cycle, the internal 7-bit address counter of the AK4634 is incremented by one,
and the next data is automatically taken into the next address so that the data can be read from the AK4634. If the address
exceeds 4FH prior to generating stop condition, the address counter will “roll over” to 00H and the data of 00H will be read
out.
Note 39. A read operation is available at 00H ~ 11H, 20H ~ 24H and 30H addresses. When reading the address 12H ~ 1FH,
25H ~ 2FH and 31H ~ 4FH, the register values are invalid.
The AK4634 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4634 contains an internal address counter that maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would access
data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4634 generates an acknowledge,
transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1.
If the master does not generate an acknowledge but instead generates stop condition, the AK4634 ceases transmission.
S
T
A
R/W="1"
R
T
SDA
Slave
S _Address
Data(n)
Data(n+1)
Data(n+2)
A
MA
MA
MA
C
AC
AC
AC
K
S
T
K
S
T
K
S
T
K
E
E
E
R
R
R
Figure 52. CURRENT ADDRESS READ
S
T
O
P
Data(n+x)
P
MA
MN
AC
AA
S
T
K
E
S
T
E
C
K
R
R
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4634 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but instead generates stop condition, the AK4634 ceases transmission.
S
T
A
R/W ="0"
R
T
S
T
A
R/W ="1"
R
T
SDA
Slave
S _Address
Sub
Address(n)
Slave
S _Address
Data(n)
Data(n+1)
A
A
A
MA
MA
C
C
C
AC
AC
K
K
K
S
T
K
S
T
K
E
E
R
R
Figure 53. RANDOM ADDRESS READ
S
T
O
P
Data(n+x)
P
MA
MN
AC
AA
S
T
K
S
T
C
E
EK
R
R
MS0686-E-03
- 60 -
2014/10