AK4634EN Datasheet, PDF (12/94 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK -AMP

[AK4634]
SWITING CHARACTERISTICS
(Ta = Tmin ~ Tmax; AVDD = 2.8  3.6V, DVDD = 1.6  3.6V, SVDD = 2.2  4.0V; C_L = 20pF)
Parameter
Symbol
min
typ
max
PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 2)
MCKI Input: Frequency
fCLK
11.2896
-
27.0
Pulse Width Low
tCLKL
0.4/fCLK
-
-
Pulse Width High
tCLKH
0.4/fCLK
-
-
MCKO Output:
Frequency
fMCK
-
256 x fFCK
-
Duty Cycle except fs=29.4kHz, 32kHz
dMCK
40
50
60
fs =29.4kHz, 32kHz (Note 20) dMCK
-
33
-
FCK Output: Frequency
fFCK
8
-
48
Pulse width High
(DIF1-0 bits = “00” and FCKO bit = “1”) tFCKH
-
tBCK
-
Duty Cycle
(DIF1-0 bits = “00” or FCKO bit = “0”)
dFCK
-
50
-
BICK: Period (BCKO1-0 = “00”)
tBCK
-
1/16fFCK
-
(BCKO1-0 = “01”)
tBCK
-
1/32fFCK
-
(BCKO1-0 = “10”)
tBCK
-
1/64fFCK
-
Duty Cycle
dBCK
-
50
-
Audio Interface Timing
DSP Mode: (Figure 3, Figure 4)
FCK “” to BICK “” (Note 21)
tDBF 0.5 x tBCK 40 0.5 x tBCK 0.5 x tBCK + 40
FCK “” to BICK “” (Note 22)
tDBF 0.5 x tBCK 40 0.5 x tBCK 0.5 x tBCK +40
BICK “” to SDTO (BCKP = “0”)
tBSD
-70
-
70
BICK “” to SDTO (BCKP = “1”)
tBSD
-70
-
70
SDTI Hold Time
tSDH
50
-
-
SDTI Setup Time
tSDS
50
-
-
Except DSP Mode: (Figure 5)
BICK “” to FCK Edge
tBFCK
40
-
40
FCK to SDTO (MSB)
tFSD
70
-
70
(Except I²S mode)
BICK “” to SDTO
tBSD
70
-
70
SDTI Hold Time
tSDH
50
-
-
SDTI Setup Time
tSDS
50
-
-
Unit
MHz
ns
ns
kHz
%
%
kHz
ns
%
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS0686-E-03
- 12 -
2014/10