AK4634EN Datasheet, PDF (16/94 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK -AMP

[AK4634]
Parameter
Symbol
min
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN edge to CCLK “” (Note 25)
CCLK “” to CSN edge (Note 25)
CCLK “” to CDTIO (at Read Command)
tCCK
200
tCCKL
80
tCCKH
80
tCDS
40
tCDH
40
tCSW
150
tCSS
50
tCSH
50
tDCD
-
CSN “” to CDTIO (Hi-Z) (at Read Command)
(Note 26)
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
tCCZ
-
fSCL
-
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 27)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive Load on Bus
Cb
-
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Reset Timing
PDN Pulse Width
(Note 28)
tPD
150
PMADC “” to SDTO valid (Note 29)
ADRST bit = “0”
tPDV
-
ADRST bit = “1”
tPDV
-
Note 24. I²C-bus is a trademark of NXP B.V.
Note 25. CCLK rising edge must not occur at the same time as CSN edge.
Note 26. R_L = 1kΩ/10% change (Pull-up to DVDD)
Note 27. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 28. The AK4634 can be reset by the PDN pin = “L”
Note 29. This is the count of FCK “” from the PMADC = “1”.
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1059
291
max Units
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
70
ns
70
ns
400
kHz
-
s
-
s
-
s
-
s
-
s
-
s
-
s
0.3
s
0.3
s
-
s
400
pF
50
ns
-
ns
-
1/fs
-
1/fs
MS0686-E-03
- 16 -
2014/10