AK4634EN Datasheet, PDF (10/94 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK -AMP

[AK4634]
Parameter
min
typ
max
Unit
Speaker-Amp Characteristics: SDTI  SPP/SPN pins, ALC2 bit = “0”, SPKG bit = “0”, R_L=8 + 10H,
BTL, SVDD=3.3V
Output Power (0dBFS)
(Note 11)
-
400
-
mW
S/(N+D)
400mW Output
-
20
-
dB
150mW Output
-
55
-
dB
Output Noise Level
-
80
70
dBV
Load Resistance
8
-
-

Load Capacitance
-
-
30
pF
Speaker-Amp Characteristics: SDTI  SPP/SPN pins, ALC2 bit = “0”, SPKG bit = “0”, C_L=3F, R_series=10 x 2, BTL,
SVDD=3.8V
Output Voltage (0dBFS)
(Note 11)
-
2.5
-
Vrms
S/(N+D) (Note 12)
-
20
-
dB
Output Noise Level (Note 12, Note 13)
-
78
-
dBV
Load Impedance (Note 14)
50
-
-

Load Capacitance
-
-
3
F
Power Supplies
Power Up (PDN pin = “H”)
All Circuit Power-up Except Video Amp: (Note 15)
AVDD+DVDD
fs = 8kHz
-
9
-
mA
fs = 48kHz
-
12
18
mA
SVDD: Speaker-Amp Normal Operation (No Output, R_L=8 + 10H)
SVDD = 3.3V
-
1.5
2.5
mA
Power Down (PDN pin = “L”) (Note 17)
AVDD+DVDD+SVDD
-
1
5
A
Note 6. The voltage difference between MICP and MICN pins. AC coupling capacitor should be inserted in series at each
input pin. Full-differential mic input is not available at MGAIN3-0 bits = “1000” or “0000”. Maximum input
voltage of MICP and MICN pins are proportional to AVDD voltage, respectively.
Vin = |(MICP)  (MICN)| = 0.069 x AVDD(max)@MGAIN3-0 bits = “0001”,
0.035 x AVDD(max)@MGAIN3-0 bits = “0010”, 0.017 x AVDD(max)@MGAIN3-0 bits = “0011”,
0.218x AVDD(max)@MGAIN3-0 bits = “0100”, 0.097x AVDD(max)@MGAIN3-0 bits = “0101”,
0.048x AVDD(max)@MGAIN3-0 bits = “0110”, 0.024x AVDD(max)@MGAIN3-0 bits = “0111”,
0.345x AVDD(max)@MGAIN3-0 bits = “1001”
When the signal larger than above value is input to MICP or MICN pin, ADC does not operate normally.
Note 7. Output voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ)
Note 8. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)
Note 9. When a PLL reference clock is FCK pin in PLL Slave Mode, S/ (N+D) of MICADC is 75dB (typ), S/ (N+D) of
DACAOUT is 75dB (typ).
Note 10. The output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)@LOVL bit = “0”.
Note 11. The value after passing LPF (LPF : Passband is 20kHz or less, Stopband Attenuation@250kHz is –50dB or less)
Note 12. In case of measuring at between the SPP pin and SPN pin directly.
Note 13. The output noise level is -68dB(typ) when fs=48kHz and measurement frequency = 20Hz ~ 20kHz.
Note 14. Load impedance is total impedance of series resistance (R_series) and piezo speaker impedance at 1kHz in
Figure 44. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10 or more series
resistors should be connected at both SPP and SPN pins, respectively.
Note 15.PLL Master Mode (MCKI = 12MHz) and PMMP = PMADC = PMDAC = PMPFIL = PMSPK = PMVCM =
PMPLL = MCKO = PMAO = M/S = “1”. Output current from the MPI pin is 0mA.
When the AK4634 is EXT mode (PMPLL = MCKO = M/S = “0”), “AVDD+DVDD” is typically
6mA@fs=8kHz, 11mA@fs=48kHz
Note 16. In case of the resistance of class-D speaker is 8Ω+10uH. When the resistance is 3µF+10Ω x2, this value will be
3.0mA@SVDD=3.8V(typ).
Note 17. All digital inputs pins are fixed to DVDD or VSS2.
MS0686-E-03
- 10 -
2014/10