AK8185A Datasheet, PDF(6/12 Page) Asahi Kasei Microsystems – Low - Jitter Clock Generator with Integrated VCO

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AK8185A Datasheet, PDF (6/12 Pages) Asahi Kasei Microsystems – Low - Jitter Clock Generator with Integrated VCO

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AK8185A

Typical Output Phase Noise Characteristics

All specifications at VDD=VDD_LVDS=VCP= 3.3Vï±5%, Ta: -40 to +85â, unless otherwise noted

Parameter

Conditions

MIN

TYP

MAX Unit

250MHz LVCMOS Input Characteristics

Phase Noise @ 100Hz offset

@ 1kHz offset

@ 10kHz offset

@ 100kHz offset

@ 1MHz offset

@ 10MHz offset

@ 20MHz offset

RMS Phase Jitter

10kHz to 20MHz

625MHz LVPECL Output Characteristics

Phase Noise @ 100Hz offset

@ 1kHz offset

@ 10kHz offset

@ 100kHz offset

@ 1MHz offset

@ 10MHz offset

@ 20MHz offset

RMS Phase Jitter

10kHz to 20MHz

625MHz LVDS Output Characteristics

Phase Noise @ 100Hz offset

@ 1kHz offset

@ 10kHz offset

@ 100kHz offset

@ 1MHz offset

@ 10MHz offset

@ 20MHz offset

RMS Phase Jitter

10kHz to 20MHz

-85

-113

-123

-125

-136

-154

384

-77

-105

-114

-117

-128

-150

-151

387

-77

-105

-114

-117

-127

-150

-152

395

dBc/Hz

ps, RMS

dBc/Hz

ps, RMS

dBc/Hz

ps, RMS

draft-E-02

Dec. 2012

-6-

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