AK8185A Datasheet, PDF (1/12 Pages) Asahi Kasei Microsystems – Low - Jitter Clock Generator with Integrated VCO

AK8185A
Low - Jitter Clock Generator with
Integrated VCO
-Preliminary-
AK8185A
- Features -
Low Phase Noise PLL
RMS jitter 0.4ps typ. (12kHz to 20MHz)
On chip VCO
4x Output Available
Pin-Selectable
LVPECL, LVDS, or 2-LVCMOS
LVCMOS Bypass Output Available
3.3V for Core
Operating Temperature Range: -40 to +85℃
Pin Package: 5mm x 5mm
32-pin Leadless QFN (Pb-free)
- Description -
AK8185A is a Low – Jitter Clock Generator with
sub pico-second jitter performance.
Also Low power consumption is the advantage
for advanced optimized application.
- Application -
Ethernet
SONET
Fibre Channel
SAN
Cost-Effective High-Frequency Crystal Oscillator
Replacement
- Block Diagram -
Vcc_IN Vcc_PLL1 Vcc_PLL2
Vcc_VCO Vcc_VDD Vcc_OUT
Input Frequency Range:
21.875MHz-28.47MHz
XIN
XO /
LVCMOS
Phase
Frequency
Detector
+15
+20
+24
+25
Feedback
Divider
VCO
RSTN
Charge
Pump
Loop
Filter
LVCMOS
Output Frequency Range:
43.75MHz-683.264MHz
+3
+4
+5
Prescaler
Divider
+.1
.
.
+4
+6
+8
Output
Divider
Output
Driver
LVPECL
LVCMOS
LVDS
LVPECL
LVCMOS
LVDS
LVPECL
LVCMOS
LVDS
LVPECL
LVCMOS
LVDS
PR[1...0]
OD[2...0] OS[1...0]
draft-E-02
Fig. 1
-1-
Dec. 2012